1. Field of the Invention
The present invention pertains in a general manner to the field of integrated-circuit digital electronic systems, called “Systems on a Chip” or SoC.
2. Description of the Related Art
More particularly, the invention relates to the management of the freezing of a functional module with the aim, for example, of waiting for the end of the execution of an operation by another functional module.
In a system on a chip, resources are conventionally shared between functional modules that have access thereto. A functional module such as this is sometimes called a virtual component or “Intellectual Property” block, or else IP block in the jargon of the person skilled in the art. It is designed to undertake a determined function, or is for general use (it may possibly be a microprocessor or a microcontroller). It can be embodied in the form of hardware elements and/or of software elements.
A distinction is made between modules of master type (hereinafter initiator modules), which take the initiative in exchanging data with one or more other modules, and modules of slave type (hereinafter target modules), whose role is to respond to the requests received from the initiator module which is in charge. Should there be a plurality of initiator modules, an arbitration unit (or arbiter) is responsible for arbitrating in respect of conflicting requests for access to a common resource originating from distinct initiator modules, so as to grant an exclusive right of access to the resource, to a determined one of the said initiator modules.
Conventionally, the functional modules communicate via at least one communication bus comprising a data bus, an address bus and a control bus. The processing of the request may begin with the implementation of a link setup procedure with mutual acknowledgements (otherwise known as “handshake”). The expression link setup procedure is understood to mean a procedure in the course of which the initiator module and the target module exchange control signals, until they are ready for the mutual transmission of data.
Nevertheless, there exist functional modules, in particular of initiator type, which make no provision for such a link setup procedure. To ensure high speed operation, certain initiator modules may in fact be designed to collect the response information from the target module by reading the data bus after a determined duration following the sending of an access request. This determined duration may be as brief as the duration of a clock cycle of the initiator module.
For example, the ST7 microcontroller from STMicroelectronics is designed to send a data read request by depositing on the address bus the address of the register targeted on an active edge of its activation signal (clock signal of the ST7), and to read the data present on the data bus (which are always assumed to be the data present) on the next active edge of the said activation signal, with no synchronization with the operation of the target module.
Such a protocol obviously operates only if the target module is fast enough to process the request within the duration of a cycle of the clock signal of the ST7. Such is not always the case in practice.
Moreover, if the target module provides for the execution of a link setup procedure before processing the request, then an interface and control module must be provided so as to effect the interface between the initiator module and the target module. The implementation of the link setup procedure between the interface module and the target module may take more time than the standby duration for which the initiator module waits (for example, for the ST7 microcontroller, the duration of a cycle of its clock signal).
In order to circumvent these difficulties, consideration may be given to “freezing” (that is to say disabling) the initiator module until the processing of the request by the target module is terminated, by including an instruction provided for this purpose in the microcode executed by the initiator module, subsequent to the instruction corresponding to the request. Such a freeze instruction exists in the instruction set of most microcontrollers and microprocessors. It is provided and used, in general, for placing the component in a standby mode or “frozen” mode, so as to reduce its energy consumption. For the ST7 microcontroller, these are for example the “WAIT” or “HALT” modes.
The execution of the freeze instruction may conventionally cause the blocking of the clock signal of the initiator module at the level of a module for generating clock signals of the system.
Nevertheless, the execution of the freeze instruction may itself take several clock cycles. In particular, the freezing of the microcontrollers and of the microprocessors requires the saving of their execution context, which must thereafter be restored during the “wakeup” (that is to say the re-enabling) of the component.
This implementation by software is therefore time and energy consuming, both in respect of the freezing and the waking up of the initiator module. It also follows that the actual freezing of the initiator module may occur too late, that is to say after the initiator module has read the data present on the data bus, wrongly believing it to be response data originating from the target module. The system is thereafter exposed to a risk of malfunctions.